Generally, semiconductor manufacturing processes have used technology having a sub-micron unit of precision to obtain semiconductor devices having excellent operational performance and a high level of integration. A reduced size of the semiconductor device may be accomplished by reducing horizontal and vertical dimensions of the device, thereby providing a balanced characteristic of the semiconductor device. If the dimensions of the semiconductor device are reduced without considering this fact, a length of the channel between a source and a drain is shortened to provide an undesired characteristic change of the semiconductor device. The representative characteristic change is a short channel effect.
To solve the short channel effect, it would be necessary to perform a horizontal reduction such as a length reduction of a gate electrode and a vertical reduction as well, such as the reductions of a thickness of a gate insulating layer and a depth of a junction of source/drain. Also, it would also require a reduction of power voltage applied, an increase of doping concentration of a semiconductor substrate, and an effective control of doping profile of a channel region, particularly.
However, because operational power required by electronics goods is not yet lowered (although the dimension of the semiconductor device is reduced), in case of, for example, NMOS transistor, it has a defective structure that may cause a hot carrier situation in which electrons from the source are considerably accelerated due to high potential gradient of the drain. Thus, a Lightly Doped Drain (LDD) has been proposed to improve NMOS transistor suffering from hot carrier effects. LDD transistor is constructed so that a lightly doped (n−) region thereof is positioned between a channel and a heavily doped (n+) drain/source. The lightly doped (n−) region serves to buffer high drain voltage around the drain junction so as not to cause a rapid change of electric potential, which restricts hot carriers. While a manufacturing method for high-integrated semiconductor device has been studied, various technologies for manufacturing an LDD structured Metal Oxide Semiconductor Field Effect Transistor (MOSFET) have been proposed. Among them, a method for manufacturing an LDD in which a spacer is formed on a sidewall of a gate electrode is a typical method. The method has been widely adapted to a technology for mass production to date. Also, in order to complement technical problems of the manufacturing method for LDD, U.S. Pat. No. 5,872,376 has proposed a method for manufacturing LDD in which a thin film of silicon layer is deposited on a buffer oxide layer so as to prevent a degradation of electric property of LDD structure.
A conventional method for manufacturing a semiconductor device will be now explained. As shown in FIG. 1, an isolation layer 102 is formed on a field region of a semiconductor substrate 101 in order to electrically insulate between, for example, active regions of the first conductive-p type semiconductor substrate 101 using a shallow trench isolation (STI) process. A gate insulating layer 103, for example, an oxide layer is grown on the active region by a thermal-oxidation process.
Then, a poly-crystal silicon layer for a gate electrode 104 is deposited on the gate insulating layer 103 by a low pressure chemical vapor deposition (CVD) process. Patterns of gate electrode 104 are formed as to be spaced apart with a predetermined distance using a photolithography. Of course, the gate electrode 104 can be composed of single layered poly silicon layer or of poly silicon layer and a silicide layer thereon.
Then, second conductive impurities such as P are ion-implanted to be lightly doped (n−) on the semiconductor substrate 101 in the active region in order to form a lightly doped (n−) region for LDD structure. Herein, the gate electrode 104 is also ion-implanted as to be lightly doped (n−) with impurities such as P.
As shown in FIG. 2, when the gate electrode 104 has been formed, a certain thermal oxidation process is performed to recover a damaged gate insulating layer due to a dry-etching of the gate electrode. Then, an oxide layer 105 for a spacer 107 of FIG. 4 is deposited in a thin thickness of about 200 Å on the gate insulating layer 103. Herein, the oxide layer 105 is formed by O3-Tetra-Ethyl-Ortho-Silicate (TEOS) CVD process or Plasma CVD process. Then, a nitride layer 106 for spacer 107 is deposited in a thickness of 800 to 1000 Å on the oxide layer 105 by low pressure CVD process.
As shown in FIG. 3, when the nitride layer 106 has been formed, using a Reactive Ion Etching (RIE) process with anisotropic etching property as an etch back process, the nitride layer 106 is dry-etched until the oxide layer 105 on the semiconductor substrate 101 in the region for source/drain and the gate electrode 104 is exposed. Herein, the nitride layer 106 remains still on the sidewalls thereof.
As shown in FIG. 4, the oxide layer 105 is dry-etched by dry etching process until the semiconductor substrate 101 in the region for source/drain and the gate electrode 104 are exposed. Thus, the oxide layer 105 remains on the sidewalls of the gate electrode 104 masked by the nitride layer 106. Accordingly, a spacer 107 consisting of the nitride layer 106 and the oxide layer 105 is formed.
Then, second conductive impurities such as P are ion-implanted to be heavily doped (n+) on the semiconductor substrate 101 in the active region that is not masked by the spacer 107 in order to form a heavily doped (n+) source/drain. Herein, the gate electrode 104 is also ion-implanted to be heavily doped (n+) with impurities such as P. Accordingly, LDD structure source/drain (not shown) is formed around the gate electrode 104 of the semiconductor substrate 101.
However, in the conventional method for manufacturing a semiconductor device, in order to recover a damaged gate insulating layer after the patterning of the gate electrode, certain thermal oxidation process is performed so that a certain oxide layer is formed on the sidewalls of the gate electrode and on the substrate. Herein, considering a recovery of the damaged gate insulating layer, the thicker the oxide layer on the sidewalls of the gate electrode is, the better the effect thereof is. On the contrary, considering an aim for minimizing substrate damage due to subsequent ion implantation, the thinner the oxide layer on the substrate is, the better the effect thereof is.
As described above, there are conflicting reasons to control thickness of the oxide layer on the substrate and on the sidewalls of the gate electrode. In the conventional method, the thickness control has been performed in consideration of correlation between the two cases.
However, in the conventional method, besides two factors for determination of the thickness of the oxide layer, an implementation of a photolithography for control of line width of a gate is not considered as another important factor. That is to say, in order to secure process margin in the subsequent control of line width of the gate, it is advantageous that the oxide layer on the sidewalls of the gate electrode is thicker, which should be considered upon forming an oxide layer by re-oxidation process.